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GW48-PK2++
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ϵy(tng): dģK USB-Blaster JTAGd ByteBlasterMVd,܌(du)ͬ˾FPGA/CPLD51ƬC(j)ھ; ԴģK (ni)Դ(bio)(zhn)+/-12V5V3.3V2.5V1.5VϹ늉ݔ·ģK ^do(h)_P(gun)Դ @ʾӿģK LED(sh)aP(yng) 10Iݔ_(d)32λM(jn)Ɣ(sh) 12(g)Ì(sh)(yn)ƽ_P(gun)3(g);I ga·ģKֱͨgaBCDga16M(jn)ga 20X4ַҺ,4*4IP M(jn)늙C(j)M(jn)вM(jn)(x)ֿƌ(sh)(yn) ֱ늙C(j)]h(hun)D(zhun)ٿϵy(tng)}_Ӌ(j)(sh)ṩ}_Ӳ(dng)O(sh)Ӌ(j) (sh)֜ضȜyģK ɈD@ʾܵVGAӿڣ (bio)(zhn)PS/2(bio)ӿںPS/2IPӿڸ1(g) RS232нӿڣʾ(sh)C(sh)˹ܣ CPLD3032ӿģK (sh)ģ惦(ch)ģK A/DD/Aӿڣ D/AcLM311(gu)ɵFPGAɿA/DO(sh)Ӌ(j)(xing)ĿģK DDS(sh)l(f)õķƫ{(dio)CģK ԴV·ΰl(f)O(sh)Ӌ(j)֮ EƽROM(sh)(yn)?zi)KIƽC惦(ch)(sh)(yn)?zi)K U(ku)չģK ģMEDAispPACm DDS(sh)l(f)ӿ U(ku)չIOģK CPLD/FPGAfܽӿģK r(sh)ԴģK 4M20MHz1Hz(bio)(zhn)lʌl̖(ho)Դ
ԴUARTͨ|ϵy(tng)d|U(ku)չBӾ m̖(ho)GWA1C6A ӲYԴ Cyclone FPGA 1C6Q24032fT 8MFLASH1MSRAM; FPGA늱o(h)4M Flash10f؏(f)̴Δ(sh)ҿɼܛǶʽϵy(tng)(sh)(j)惦(ch) ӿYԴ JTAGASd USBӿ PS/2IPPS/2(bio)ӿڣ 8ɫVGAһ(g) 512KB SRAM֮VGA@ʾ棻 ̫W(wng)ڣ EPM3032A CPLD RS2321(g) SDӿɽ1-2GB Flash 20MHzr(sh)Դɱl300MHz1(g) Zɘӿڣ wݔڣ MICģMݔ ٕr(sh)犿һ(g) IOU(ku)չ 8051 IP ˽ӿڣ pͨDACADCӿ m̖(ho)GW_ADDA ӲYԴ 180MHzD(zhun)Qr(sh)p·10λDAC 50MHzͨ8λADC; 300MHzن\(yn)2(g); Õr(sh)ݔ EDA(sh)(yn)(xing)Ŀ 8λȫ(sh)(yn) 2x1·x 4λӷӋ(j)(sh) 8λӲ/p O(sh)Ӌ(j) O(sh)Ӌ(j); 7gaO(sh)Ӌ(j) (sh)طl; ؓ(f)}{(dio); λĴ; ̖(ho)l(f); 8λ16M(jn)lӋ(j); Йzy; B(ti)C(j)ADCɘ; ^DA(sh)F(xin)AD; RAMԶƌ(sh)(yn) ROMԶƌ(sh)(yn); FIFO(sh)(yn); ȵ C/(yng)_l(f)(sh)(yn) A/D(sh)(j)ɼ·ͺ״惦(ch)ʾO(sh)Ӌ(j) λӲ˷O(sh)Ӌ(j); Ӳ·O(sh)Ӌ(j) VGAD@ʾO(sh)Ӌ(j) DDSֱӔ(sh)ʽlʺϳO(sh)Ӌ(j) PS/2IP(bio)ģKO(sh)Ӌ(j) FPGAcRS232ͨģKO(sh)Ӌ(j) USBcFPGAͨŌ(sh)(yn) xSD(sh)(yn) ڠB(ti)C(j)16λCPUO(sh)Ӌ(j)c(sh)F(xin) DDSO(sh)Ӌ(j)(sh)(yn) ȾȔ(sh)l/λyԇxO(sh)Ӌ(j)(sh)(yn) ̖(ho)ɼclV·O(sh)Ӌ(j) A/DD(zhun)Qܵ·O(sh)Ӌ(j) D/Aΰl(f) ˮg(sh)O(sh)Ӌ(j)ٔ(sh)P(gun) ӲO(sh)Ӌ(j) ƹΑ·O(sh)Ӌ(j) M(jn)늙C(j)(x)(q)(dng)O(sh)Ӌ(j) VGAʗl̖(ho)@ʾO(sh)Ӌ(j) VGAD@ʾO(sh)Ӌ(j)Α Ƕʽih(hun)PLL(yng)Ì(sh)(yn) PS/2(bio)cVGA@ʾΑģKO(sh)Ӌ(j) FPGA_ƬC(j)_PCC(j)pͨŜylģKO(sh)Ӌ(j) ɫҺc(din)Αƌ(sh)(yn) ɫҺ(j)Αƌ(sh)(yn) 8λCPUO(sh)Ӌ(j)c(sh)F(xin) ˮ(gu)ܵ16λRISC CPUO(sh)Ӌ(j)c(sh)F(xin) 惦(ch)ʾO(sh)Ӌ(j) 10·߉xO(sh)Ӌ(j) IPˌ(sh)(yn) 8051ƬC(j)IPϵO(sh)Ӌ(j)(sh)(yn)9t (sh)ʎNCO(yng)O(sh)Ӌ(j) FFT(yng)O(sh)Ӌ(j) FIR(sh)֞V(yng)O(sh)Ӌ(j) Ƕʽ߉xSignalTapII{(dio); DSPBuilder(sh)(yn) ̖(ho)l(f)O(sh)Ӌ(j) ̖(ho)l(f)O(sh)Ӌ(j) FSK{(dio)O(sh)Ӌ(j) {(dio)c{(dio)ģO(sh)Ӌ(j)(sh)(yn) FIR(sh)֞VO(sh)Ӌ(j)(sh)(yn) DDSc(sh)̖(ho)l(f)O(sh)Ӌ(j)(sh)(yn) Ϳ˴azO(sh)Ӌ(j)(sh)(yn) IIR(sh)֞VO(sh)Ӌ(j)(sh)(yn); mЂSC(j)аl(f)O(sh)Ӌ(j)(sh)(yn) RSaaO(sh)Ӌ(j)(sh)(yn) SOPC(sh)(yn) ˮ UART(yn)C(sh)(yn) r(sh)Д(sh)(yn) SOPCO(sh)Ӌ(j) Nios/IIVGA@ʾKO(sh)Ӌ(j) c(din)ҺO(sh)Ӌ(j) ɫҺO(sh)Ӌ(j) SOPCGPSϵy(tng)(sh)(yn) PWM늙C(j)D(zhun)ٌ(sh)(yn) r(sh)(yn)C(sh)(yn) GSMģKO(sh)Ӌ(j) NiosII Avalon SlaveO(sh) PWMģKO(sh)Ӌ(j) DMA(yng)úͶ_˹KΑO(sh)Ӌ(j) ַҺO(sh)Ӌ(j) ̫W(wng)ڑ(yng)Ì(sh)(yn) ȵ |